Challenges of Porting ASIC IP Cores to FPGA

In this white paper:

• Deploying an IP core for use on both ASIC and FPGA architectures is challenging—but worthwhile
• Relevant considerations when porting and ASIC IP to FPGA include differences in requirements, performance, clocking, functionality, etc. 
• An optimal IC design solution combines both FPGAs as a prototyping vehicle and silicon-proven IP cores as a guarantee for error-free implementation
• Practical example: USB 3.2 Gen2x1 Device IP

Abstract

Manufacturers of semiconductor IP cores support complex ASIC projects, some of which include extreme requirements in terms of clock speeds, area utilization, power consumption, reliability, functional safety, and reusability—and all of which come with high expectations for predefined circuit parts. Anyone who decides not to develop a certain functionality themselves, but rather to obtain it through a partner, accepts the purchased component’s functionality as a foregone conclusion. It is assumed that the use of IP cores from reputable suppliers will go smoothly.

Since the areas of end-application for one and the same IP core can be completely different, the IP core provider must take all possible areas of application into account, in order to avoid disappointing their customers. If a function—for example, a MIPI CSI-2 Receiver/Transmitter IP or USB interface—is used in a consumer product that is sold millions of times, the requirement is different than when the IP core is used in the "hot area" of a fighter plane manufactured in limited quantities.

For one user, the definition of success might be a reduction of silicon area. For another, it could mean lowest power consumption or maximum reliability, even under harsh operating conditions. In most cases there is another important point to consider. The IP core should not only “land” on the ASIC, but also be used as part of FPGA-based prototyping. It is well understood that ASICs require a great deal of care in their development, yet sadly often underestimated that an FPGA requires very special attention as well, and in its own unique way.

To put it bluntly: porting ASIC IP cores to FPGA is not a cakewalk—but if the process is approached methodically, success is attainable! This paper outlines everything that must be considered when porting ASIC IP cores to FPGA and further illustrates these points with a practical example using SmartDV’s USB3.2 Gen2x1 Device IP.